The instant invention resides in the art of data processors and, more particularly, with large scale parallel processors capable of handling large volumes of data in a rapid and cost-effective manner. Presently, the demands on data processors are such that large pluralities of data must be arithmetically and logically processed in short periods of time for purposes of constantly updating previously obtained results or, alternatively, for monitoring large fields from which data may be acquired and in which correlations must be made. For example, this country is presently intending to orbit imaging sensors which can generate data at rates up to 10.sup.13 bits per day. For such an imaging system, a variety of image processing tasks such as geometric correction, correlation, image registration, feature selection, multispectral classification, and area measurement are required to extract useful information from the mass of data obtained. Indeed, it is expected that the work load for a data processing system utilized in association with such orbiting image sensors would fall somewhere between 10.sup.9 and 10.sup.10 operations per second.
High speed processing systems and sophisticated parallel processors, capable of simultaneously operating on a plurality of data, have been known for a number of years. Indeed, applicant's prior U.S. Pat. Nos. 3,800,289; 3,812,467; and 3,936,806, all relate to a structure for vastly increasing the data processing capability of digital computers. Similarly, U.S. Pat. No. 3,863,233, assigned to Goodyear Aerospace Corporation, the assignee of the instant application, relates specifically to a data processing element for an associative or parallel processor which also increases data processing speed by including a plurality of arithmetic units, one for each word in the memory array. However, even the great advancements of these prior art teachings do not possess the capability of cost effectively handling the large volume of data previously described. A system of the required nature includes thousands of processing elements, each including its own arithmetic and logic network operating in conjunction with its own memory, while possessing the capability of communicating with other similar processing elements within the system. With thousands of such processing elements operating simultaneously (massive-parallelism), the requisite speed may be achieved. Further, the fact that typical satellite images include millions of picture elements or pixels that can generally be processed at the same time, such a structure lends itself well to the solution of the aforementioned problem.
In a system capable of processing a large volume of data in a massively-parallel manner, it is most desirable that the system be capable of performing bit-serial mathematics for cost effectiveness. However, in order to increase speed in the bit-several computation, it is most desirable that a variable length shift register be included such that various word lengths may be accommodated. Further, it is desirable that the massive array of processing elements be capable of intercommunication such that data may be moved between and among at least neighboring processing elements. Further, it is desirable that each processing element be capable of performing all of the Boolean operations possible between two bits of data, and that each such processing element include its own random access memory. Yet further, for such a system to be efficient, it should include means for bypassing inoperative or malfunctioning processing elements without diminishing system integrity.